1. Field of the Invention
The present invention relates to packaging techniques for semiconductor dies. More specifically, the present invention relates to packaging techniques for coupling single-chip and/or multi-chip modules that include semiconductor dies that communicate signals using proximity connectors.
2. Related Art
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, it becomes possible to transmit data signals directly from the first chip to the second chip without having to route the data signals through intervening signal lines within a printed circuit board.
Capacitive coupling depends on a relative position of the transmitter pads and the receiver pads, both in a plane defined by the pads and in a direction perpendicular to the plane. Misalignment in the plane may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, for a geometry with a single transmitter and receiver pad per signal channel, and with each pad having the same size, satisfactory communication requires alignment such that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, limiting overall misalignment may improve communication performance between the chips and reduce power consumption.
Unfortunately, it is not a simple matter to align the chips properly using existing mounting structures, such as conventional single-chip modules or conventional multi-chip modules. The chips in these structures are subject to thermal expansion and mechanical vibrations, as well as manufacturing and assembly perturbations that result in misalignment problems.
Capacitively coupled inter-chip communication may offer a high-bandwidth when communicating between adjacent chips and chips that are in close proximity to one another. Latency challenges, however, may occur when communicating over longer distances, such as in a multi-chip module (MCM). This latency may impact communication between a CPU and an external cache and/or main memory, and therefore, may adversely affect the system performance.
What is needed is needed are packaging techniques for single-chip modules and multi-chip modules to facilitate capacitive inter-chip communication without the problems listed above.